1. Field of the Invention
The present invention relates to a semiconductor device prior to being divided into individual semiconductor chips, the semiconductor device having integrated circuits formed on a semiconductor wafer in a wafer processing step, and more particularly to a semiconductor device which allows bonding pads and a probe card to be positioned easily when integrated circuits on a semiconductor wafer are inspected by a wafer prober.
2. Description of the Related Art
To fabricate semiconductor devices such as ICs (integrated circuits) or the like, a number of ICs or LSI (large-scale-integration) circuits are simultaneously formed on a single semiconductor wafer, and then the semiconductor wafer is divided into a number of IC or LSI chips which contain the ICs or LSI circuits, respectively.
FIG. 1(a) of the accompanying drawings shows in perspective a semiconductor wafer (semiconductor device) prior to being divided into individual semiconductor chips, the semiconductor wafer having integrated circuits formed thereon in a wafer processing step. As shown in FIG. 1(a), the semiconductor wafer, generated denoted at 110, has a plurality of chip regions 102 defined by scribing line regions 101.
FIG. 1(b) of the accompanying drawings shows in enlarged plan an encircled portion A of the semiconductor device shown in FIG. 1(a). Usually, circuit elements such as transistors or the like are not formed in the scribing line regions 101. The chip regions 102 surrounded by the scribing line regions 101 contain circuit elements such as transistors or the like which are formed in semiconductor layers thereof, and these circuit elements make up integrated circuits. Bonding pads 103 made of metal such as aluminum or the like are formed as terminals of integrated circuits on inner peripheral edges of the chip regions 102.
In the fabrication of semiconductor devices, the integrated circuits in the chip regions 102 on the semiconductor wafer 110 shown in FIGS. 1(a) and 1(b) are inspected for their electric characteristics when the wafer processing step is finished. The test is referred to as a wafer probe test which employs a wafer prober.
After the wafer probe test, the semiconductor wafer 110 is divided into individual chips along the scribing line regions 101. The separate individual chips are then packaged by respective enclosures. The bonding pads 103 on the chips are connected to inner leads in the enclosures by wire bonding.
A wafer probe test will be described below.
First, a probe card for electrically connecting a test head of the wafer prober and an integrated circuit is fixed to the test head. As shown in FIG. 2(a) of the accompanying drawings, the probe card is in the form of a flat disk with a central opening 121 and has a plurality of conductive probes 122 projecting into the central opening 121 and a plurality of electrode pins 123 electrically connected to the respective probes 122. The electrode pins 123 are electrically connected to the test head when the probe card is fixed to the test head. As shown in FIG. 2(b) of the accompanying drawings, the probes 122 have respective tip ends positionally adjusted in the alignment with the layout of the bonding pads 103 of a chip region 102 which is to be tested.
After the probe card has been fixed to the test head, the semiconductor wafer 110 is fastened to a stage of the wafer prober. The stage is movable in X and Y directions extending perpendicularly to each other parallel to the plane of the semiconductor wafer 110, a Z direction extending perpendicularly to the plane of the semiconductor wafer 110, and a .theta. direction around the Z direction. When the semiconductor wafer 110 is fastened to the stage, the wafer prober recognizes the pattern of the desired chip region 102 on the semiconductor wafer 110. After the pattern of the chip region 102 has been recognized, the wafer prober automatically adjust the angular orientation of the stage in the .theta. direction in order to bring the X and Y directions of the stage into alignment with the directions of the scribing lines of the semiconductor wafer 110, and also roughly positions the stage so that the desired chip region 102 will be positioned in the central opening 121 of the probe card.
Thereafter, while looking through the stereomicroscope of the wafer prober, the operator makes manual fine adjustments of the position of the stage for positionally aligning the probes 122 of the probe card with the respective bonding pads 103 of the chip region 102. Specifically, such manual fine adjustments of the position of the stage are effected by moving the stage in the Z direction to bring the probes 122 against the semiconductor wafer 110 to mark the semiconductor wafer 110 with the probes 122, moving the probes 122 away from the semiconductor wafer 110, confirming the positions of the marks of the probes 122 on the semiconductor wafer 110 with the stereomicroscope, and adjusting the stage in the X, Y, and .theta. directions until the positions of all the probes 122 are aligned with the corresponding bonding pads 103.
After the manual fine adjustments of the position of the stage have been finished, the wafer prober automatically inspects successively the integrated circuits on the chip regions 102 for their electric characteristics.
Efforts have been made in the art to manufacture semiconductor products with more pins and smaller bonding pad pitches or spacings. With smaller bonding pad pitches or spacings, it becomes more difficult for the operator to find boundaries between adjacent bonding pads 103 and to see marks of the probes 122 because the probes 122 themselves are closely spaced and get in the way when the operator makes manual fine adjustments of the position of the stage using the stereomicroscope. Therefore, it is more difficult to position the probes 122 with respect to the bonding pads 103 with a high degree of accuracy. As a consequence, the probes 122 tend to be in poor contact with the bonding pads 103, resulting in a greater possibility to judge acceptable semiconductor devices as defective semiconductor devices and hence in a poor yield of semiconductor devices.
Japanese patent laid-open No. 64-73629 discloses a semiconductor integrated circuit having at least two mark pads as a positioning reference in a chip region for facilitating positioning of probes with respect to bonding pads. Specifically, the disclosed semiconductor integrated circuit comprises a chip, a circuit element disposed on the chip, a plurality of pads serving as terminals for supplying electric energy to the circuit element and transmitting input and output signals to and from the circuit element, and at least two mark pads as a positioning reference on the chip for use in bringing test probes into contact with the pads, respectively. The mark pads are positioned in the same row as the bonding pads. The test probes and the bonding pads can be accurately aligned with each other when mark pad probes, separate from the test probes, are aligned with central position of the mark pads.
Since, however, the mark pads are positioned in the same row as the bonding pads, smaller pitches or spacings between the bonding pads are liable to cause the mark pads to be concealed by test probes, with the result that the mark pad probes cannot accurately be positioned with respect to the mark pads. Another problem is that the mark pads on the chip reduce the effective availability of the area of the chip.
Furthermore, the mark pads, which only serve as a positioning reference, are not effective to check whether the probes are in actual contact with the bonding pads. Therefore, the possibility to judge acceptable semiconductor devices as defective semiconductor devices still remains with the disclosed arrangement.